This invention relates to a fabrication technology for a semiconductor device and, more particularly, to a process for fabricating a semiconductor integrated circuit device having an inter-level insulating layer of parylene polymer and a deposition system used therein.
Manufacturers have increased circuit components of an integrated circuit device, and, accordingly, scaled down the circuit components and conductive strips used as signal lines. The conductive strips are arranged at extremely narrow intervals on an insulating layer, and are covered with another insulating layer. Two adjacent conductive strips and the insulating layer therebetween form a parasitic capacitor, and the parasitic capacitor retards signal propagation along the conductive strips. The parasitic capacitance is increased inversely proportional to the gaps between the conductive strips, and the signal delay becomes serious.
The parasitic capacitance is proportional to the dielectric constant of the insulating layer. Even though the conductive strips are arranged at the extremely narrow intervals, a kind of insulating material with a small dielectric constant does not increase the parasitic capacitance.
Parylene is attractive material, and an inter-level dielectric layer of parylene is disclosed by N. Majid et. al. in xe2x80x9cExperimental Study of Parylene As Interlayer Dielectrics for Wafer Scale Interconnectionsxe2x80x9d, 1988 VLSI Multilevel Interconnection Conference Proceedings, pages 299 to 305, Jun. 13-14, 1988. Parylene is poly(para-xylylene). FIG. 1 illustrates the prior art deposition system for an insulating layer of parylene. The prior art deposition system includes a vaporizer 1, a pyrolysis unit 2, a deposition unit 3 and pipes 4a/4b connected between the vaporizer 1, the pyrolysis unit 2 and the deposition unit 3. A dimer of parylene is sublimated in the vaporizer 1 at 250 degrees in centigrade at 1 torr, and the dimer of parylene gas flows through the pipe 4a into the pyrolysis unit 2. The pyrolysis unit 2 is. maintained at 680 degrees in centigrade at 0.5 torr, and the dimer gas of parylene is cracked in the pyrolysis unit 2. Monomer gas of parylene is produced from the dimer gas of parylene, and is supplied from the pyrolysis unit 2 to the deposition unit 3. A semiconductor wafer 5 is accommodated in the deposition unit 3, and the deposition chamber is maintained at 0.1 torr. The surface of the semiconductor wafer 5 is near 25 degrees in centigrade, and the monomer of parylene is polymerized on the surface of the semiconductor wafer 5. As a result, a polymer layer of parylene is formed.
Using the polymer layer of parylene as an inter-level insulating layer, a multi-layered wiring structure is fabricated as shown in FIGS. 2A to 2E. Firstly, a semiconductor wafer 11 is prepared. Though not shown in the figures, the major surface of the semiconductor wafer 11 is covered with an insulting layer. Aluminum is deposited over the major surface of the semiconductor wafer 11, and the aluminum layer is patterned into lower conductive strips 12a/12b by using a photo-lithography and an etching as shown in FIG. 2A.
The lower conductive strips 12a/12b are covered with a polymer of parylene through the prior art deposition system shown in FIG. 1, and the polymer layer 13 of parylene conformably extends over the lower conductive strips 12a/12b as shown in FIG. 2B. Silicon oxide is deposited over the polymer layer of parylene 13 by using a chemical vapor deposition, and the silicon oxide layer is chemically mechanically polished, and a smooth surface of the silicon oxide layer 14 is created as shown in FIG. 2C. The polymer layer 13 of parylene and the silicon oxide layer 14 form in combination an inter-level insulating structure 15.
Contact-holes 15a/15b are formed in the inter-level insulating structure 15 by using the photo-lithography and an etching, and the lower conductive strips 12a/12b are exposed to the contact-holes 15a/15b. The contact holes 15a/15b are plugged with tungsten pieces 16a/16b, respectively as shown in FIG. 2D, and an upper conductive strip 17 of aluminum is patterned on the inter-level insulating structure 15 by using the deposition, the photo-lithography and the etching. The upper conductive strip 17 is electrically connected through the tungsten plugs 16a/16b to the lower conductive strips 12a/12b as shown in FIG. 2E.
The manufacturer encounters a problem in the prior art process in that the silicon oxide layer 14 peels from the polymer layer 13 of parylene. The peeling is derived from residual monomer of parylene and residual dimer of parylene in the polymer layer 13. All the dimer gas is not decomposed into monomer gas, and the residual dimer gas is carried into the deposition chamber together with the monomer gas. Moreover, the monomer is not only polymerized in the deposition chamber but also recombined into the dimer of parylene. For this reason, the dimer and the monomer are taken into the polymer layer 13 during the polymerization, and cause peeling. The residual dimers and the residual monomers are vaporized around 400 degrees centigrade during the deposition of silicon oxide layer 14 and the deposition of tungsten, and the dimer gas and the monomer gas cause the silicon oxide layer 14 to peel from the polymer layer 13 of parylene.
It is therefore an important object of the present invention to provide a process for fabricating a semiconductor device, which has a polymer layer of parylene strongly adhered to another layer.
It is also an important object of the present invention to provide a deposition system, which is used for growth of the polymer layer of parylene.
To accomplish the object, the present invention proposes to release the residual dimer/monomer gas from a polymer layer of parylene before deposition of another material over the polymer layer.
In accordance with one aspect of the present invention, there is provided a process for fabricating a semiconductor device comprising the steps of preparing a semiconductor structure having a first layer, supplying a source gas over the first layer so as to form a polymer mainly consisting of parylene over the first layer, releasing residue of the source gas from the polymer mainly consisting of parylene in a high temperature vacuum, a high temperature inert gas containing atmosphere or a high temperature nitrogen containing atmosphere and covering the polymer mainly consisting of parylene with a second layer.
In accordance with another aspect of the present invention, there is provided a vapor phase deposition system for forming a polymer layer mainly consisting of parylene on a semiconductor structure comprising a reactor having a reaction chamber where the semiconductor structure is accommodated, an evacuating sub-system connected to the reactor for creating vacuum in the reaction chamber, a gas supply sub-system connected to the reactor and supplying a source gas to the reaction chamber for forming a polymer layer mainly consisting of parylene over the semiconductor structure and a gas releasing means for releasing residue of the source gas from the polymer layer mainly consisting of parylene in a high temperature vacuum, a high temperature inert gas containing atmosphere or a high temperature nitrogen containing atmosphere.